FPGA Implementation of a Fix-Point Digital Baseband Pre-Distorter for the Linearization of Wireless Transmitters

Digital baseband predistortion (DPD) is a cost effective solution to improve the energetic efficiency of power amplifiers (PA) for wireless communication systems. This paper addresses the design of DPD in fix-point arithmetic, suitable for real-time implementation in a low-cost hardware such as a Field Programmable Gate Array (FPGA). The design starts in floating-point double-precision arithmetic for the parameter identification of a DPD having a memory polynomial topology. Then, the not straightforward conversion to fix-point arithmetic is discussed. The presented fix-point design allows for the realtime applicability of the DPD, by processing the polynomials as Look-Up-Tables (LUT) and by using a sequential logic circuit that exploits as much as possible the parallel processing. For the FPGA Xilinx Virtex 5 and for numbers having 16 bits, it was verified that a DPD frequency as high as 60 MHz can be used and the DPD power consumption is approximately 0.5 W. The validation of the accuracy of the designed fix-point DPD is done based on computer simulations performed on a PA behavioral model excited by a 3GPP WCDMA signal. It is verified that, if the PA is operated with a constant average output power in the cases with and without DPD, then the inclusion of the DPD improves the ACPR metric at the PA output by 25 dB. Index Terms — FPGA, linearization, memory polynomial, power amplifiers, VHDL language.